1. Field of the Invention
The present invention relates to frequency tracking in fractional-N phase-lock-loops (PLLs) and more specifically to the suppression of fractional spurs which are present in conventional implementations of both fixed band and multi-band fractional-N PLLs.
2. Brief Description of the Prior Art
PLL based frequency synthesizers are one of the key components in wireless transceivers. Some of the critical parameters of a PLL for wireless applications are switching time, phase noise, and reference feed-through. In the case of time-division multiple access (TDMA) systems, fast switching time from one channel (frequency) to another is required to meet time-slot conditions. Fast switching times can also result in reduced power dissipation which is important in portable systems.
FIG. 1 shows a typical architecture for the type conventional integer-N PLL used predominantly in the wireless market today. In this conventional scheme, N is an integer number. In this circuit, the reference frequency f.sub.R, which is divided down by reference divider 2 from the crystal 1, drives the phase detector 3 as does the feedback signal f.sub.V, which is the output frequency f.sub.O from the voltage controlled oscillator (VCO), divided by integer N in the main divider 7. The output of the charge pump 4 is coupled to filter 5 to provide a voltage to the VCO 6 so that the relation f.sub.O =N*f.sub.R exists when the PLL is locked. One problem with such a circuit is that reference spurious sidebands exist which tend to show up in the output spectrum.
Fractional-N PLL synthesizers represent another category where the division ratio, N, takes on fractional values. In this case, the output frequency, f.sub.O, is stepped in x/m fractions of the reference frequency. A common technique used to realize this is to divide by N+1 every m cycles and then divide by N the rest of the time so that the effective fractional ratio is: ##EQU1##
where x=0, 1, 2, . . . m-1.
The direct implementations of this technique is the potential improvement of the phase noise and switching speed compared to the integer-N PLL discussed above. That is, for the same output frequency f.sub.O, if f.sub.R is increased m times, the division ratio is scaled down by the same m factor, resulting in lower phase noise. In addition, since f.sub.R is higher, the loop bandwidth can be made wider so that faster lock time can be realized. Although with fractional-N synthesizers the reference spurs still exist in the output spectrum, they are moved further from the carrier frequency which is an improvement. FIG. 2 shows a block diagram for a typical fractional-N synthesizer. The circuit looks much like that for integer-N synthesizer discussed above, but now the main divider 7 is capable of switching from divide by N to divide by N+1. The divisor ratio is switched from N to N+1 by the overflow signal from an L-bit accumulator 8 which is added to the circuit. The value for the fractional modulus m is given as 2.sup.L =m, where L is the number of bits in the accumulator. This accumulator is clocked by f.sub.V and is incremented in steps of x, where x is 1, 2, . . . m-1 so that an overflow occurs at a rate of x/m. Typical results for this type circuit is as follows:
f.sub.R =240 KHz PA1 x=1 PA1 L=3 (bits) PA1 M=2.sup.L =8 PA1 Channel spacing=30 KHz ##EQU2##
As mentioned above, there is still the problem of fractional spurs associated with this fractional-N PLL synthesizer. With the PLL in lock condition, there is an instantaneous phase error at the input to the phase detector as shown in FIG. 3. This error generates small charge pump current pulses which tend to ramp the control voltage of the VCO. If this error is not canceled, fractional spurious sidebands at ##EQU3##
will show up in the output frequency spectrum. To suppress these spurious sidebands, fractional-N synthesizers often have internal compensation circuitry, which generates complementary fractional waveforms, to cancel (reduce) the phase error. Using this technique, spurs can be reduced to better than 60 dB.
FIG. 4 shows a typical architecture for a scheme used to cancel the spurs by developing a fractional charge pump compensation signal. This compensation circuitry is used in the analog domain and is based on pulse amplitude modulation (PAM) of the compensating charge pump current pulses. In this case the pulses have constant width and their amplitude is modulated. The content of the L-bit accumulator 8 is feed through a digital-to-analog converter (DAC) 9 and used to modulate the amplitude of the compensation current, which is generated by a fractional charge pump 10. Special fractional timing circuitry 11, driven by the f.sub.V signal from main divider 7, generates the fractional compensation pulse which drives fractional charge pump 10. The theory is that the PAM output from the fractional charge pump 10 cancels the spurious PWM signals from the main charge pump 4. In practice, this results in effective spur suppression as long as the charge (q), or area under each compensating current pulse, is equally matched to the equivalent charge or area of the main charge pump 4 current pulses.
The conventional techniques for spur suppression discussed above, where the fractional timing circuitry is driven at a constant rate from crystal 1 and as a result has a fixed width, works fairly well for single channel, fixed band applications. Since the compensation circuitry 11 does not track the VCO 6 frequency, even for fixed band applications where the frequency may vary as much as 10% when switching from receiver (Rx) to transmitter (Tx) operation, there can be imperfect sideband spurious suppression. However, in dual channel applications, where the frequency bands may change from one band at 900 MHz to another at 1900 MHz or higher, this technique is not effective. The present invention addresses this problem by generating a precise fractional pulse width which has VCO tracking characteristics. The compensation circuitry for this new fractional-N PLL synthesizer approach tracks the variations in the f.sub.O signal at the output of the VCO 6. This is important for both dual band applications where there are large frequency changes and for fixed band applications where f.sub.O may have smaller variations around the fixed frequency.